1. Field of the Invention
The present invention relates to a write operation of a synchronous dynamic random access memory (DRAM), comprising a 2-bit pre-fetch function, and more particularly, to a semiconductor memory device capable of shortening write time.
2. Description of the Related Art
A synchronous DRAM receives in synchronous with a clock an address and control command from a system that controls memory, and performs internal read and write operations in synchronous with the clock. As a result, it makes possible highspeed memory operations.
Furthermore, for an externally-supplied column address, synchronous DRAM comprises a burst mode function, which accesses the memory cell of that column address, and a column address subsequent thereto. In this burst mode, a synchronous DRAM can perform read or write operations by accessing the memory cells of sequential column addresses of 2-bits, 4-bits or 8-bits from the supplied column address according to the burst length.
To make this burst mode even more efficient, a 2-bit pre-fetch function is incorporated. A 2-bit pre-fetch function latches a supplied column address or an internally-generated first column address, generates a second column address by adding 1 bit to that first column address, and accesses a memory cell with a first and second column address. The memory cell array side comprises an odd memory cell array with a corresponding column address decoder and output data hold circuit, and an even memory cell array with a corresponding column address decoder and output data hold circuit. When the first column address is even, the first column address is applied to the even column address decoder, and the second column address is applied to the odd column address decoder, respectively. And when the first column address is odd, the first column address is applied to the odd column address decoder, and the second column address is applied to the even column address decoder, respectively. Then, data is sequentially output to the outside, either from even data to odd data, or from odd data to even data. Or, when writing, either even data and odd data are written in that order together with the even first column address, or odd data and even data are written in that order together with the odd first column address.
As described above, in a synchronous DRAM, a control signal and an address signal are generally applied from outside in synchronous with a clock, and internally, various operations are performed in synchronous with a clock.
However, for a write operation, external write data must be applied to a memory data input-output terminal (DQ terminal). This data input-output terminal differs from a command signal and address signal input terminal in that it has a large load carrying capacity. The reason for this is that command signal and address signal input terminals are dedicated input terminals, and as such, their internal circuitry is connected only to input circuits. By contrast, the load carrying capacity of a data input-output terminal is large because it is connected to both input circuitry and output circuitry.
Therefore, the system is capable of applying a command signal and address signal in synchronous with a clock relatively easily. However, when a write data signal is applied to a data input-output terminal with a large load carrying capacity, that data signal undergoes rounding, making it difficult to furnish memory with a data signal that is accurately in synchronous with the rising edge or falling edge of the clock. That is, a command signal and address signal can be accurately applied to a command signal and address signal input terminal that has a small input load capacity, by using a common clock as a strobe signal. However, from the standpoint of specifications, it is difficult to apply a write data signal to a data input-output terminal that has an input load capacity larger than the above input terminal by using the same clock as a strobe signal. Moreover, it is even more difficult to apply a write data signal at high speed in synchronous with the rising edge and falling edge of a clock.
Thus, it was proposed that the system supply a write data signal in synchronous with a data strobe signal that is not in synchronous with the clock. This data strobe signal has the same frequency as the clock, but is not phase synchronousronized with the clock.
It is thus necessary to solve the problem of how to control an internal write operation in line with the introduction of a data strobe signal that is not in synchronous with the clock. A proposal has yet to be made for using an externally-applied clock and data strobe signal to perform an optimum write operation.
Thus, to solve the problems of the past described above, an object of the present invention is to provide a semiconductor memory device capable of performing an optimum write operation using a clock and a data strobe signal that is asynchronous thereto.
Further, a separate object of the present invention is to provide a semiconductor memory device capable of performing the shortest write operation using a clock and a data strobe signal that is asynchronous thereto.
Further, it is a separate object of the present invention to provide a semiconductor memory device capable of shortening a write operation in a memory, to which command, address, and write data signals are supplied in synchronous with a clock.